The present disclosure relates to a dynamic random access memory (DRAM) structure, and particularly to a DRAM structure including an asymmetric stressor and a method of manufacturing the same.
Generally, low leakage current is desirable in a DRAM cell in order to provide long retention time for the electrical charge stored in a capacitor. However, in the case of a DRAM cell formed on a semiconductor-on-insulator (SOI) substrate, excessively low leakage current can induce a floating body potential problem in which the voltage of the body of an access transistor is not predictable, and thus, the threshold voltage of the access transistor becomes unstable.